1. Field of the Invention
The present invention relates to a circuit for generating a step-up voltage in a non-volatile memory device. More particularly, to a circuit for generating a step-up voltage necessary upon Incremental Step Pulse Programming (ISPP).
2. Discussion of Related Art
Non volatile memory devices, such as a flash memory or EEPROM devices, require a step-up voltage whose voltage level gradually rises upon ISPP. The step-up voltage is internally generated using a voltage higher than an external power supply voltage.
FIG. 1 is a circuit for implementing ISPP employing an externally applied high voltage 25V. It is assumed that the ISPP specification ranges from 16.5V to 21V and a step voltage (STEP) is 0.5V.
Referring to FIG. 1, if an enable signal (EN) is enabled, the external high voltage 25V is output to an output terminal Vout. At this time, to implement the ISPP method, step-up reference voltages (TISPP<7:0>; which may be extended or shortened depending on a step number) are activated from TISPP<0> to TISPP<7> at given intervals. Voltages V0 to V7, which are obtained by dividing the step-up voltage of the output terminal Vout using resistors R1 to R9, are feedback voltages. The voltages V0 to V7 are input to a comparator 11 through NMOS transistors N1 to N8 driven by the step-up reference voltages (TISPP<7:0>), respectively.
The comparator 11 outputs the output signal (Vcom) as a logical low if the level of the feedback voltages V0 to V7 is higher than that of a bandgap reference voltage (Vbg), which is set to 1V. A NOR gate NR1 performs a NOR operation on the output signal (Vcom) of a logical low and an output signal of an inverter IV1 of a logical low, and makes a node LEAK a logical high. A NAND gate ND1 performs a NAND operation on a clock signal (CLK) and the output signal (Vcom) of a logical low and fixes an internal clock signal (CLK1) to a logical high.
At this time, a high voltage switching unit 12 stops the operation of pumping a high voltage (VPP) using the internal clock signal (CLK1) fixed to a logical high. NMOS transistors N11 to N16 are all turned on to connect a driving node SEL of a high voltage NMOS transistor N10 to the ground (VSS). In this case, the high voltage NMOS transistor N10 is turned off, so that a step-up voltage level of the output terminal Vout is lowered.
Meanwhile, if the level of the feedback voltage (V0 to V7) is lower than that of the bandgap reference voltage (Vbg), which is set to 1V), the comparator 11 outputs the output signal (Vcom) as a logical high. The NOR gate NR1 then performs a NOR operation on the output signal (Vcom) of a logical high and the output signal of the inverter IV1, of a logical low, and makes a node LEAK a logical low. The NAND gate ND1 performs a NAND operation on the output signal (Vcom) of a logical high and the clock signal (CLK), and toggles the internal clock signal (CLK1).
At this time, the high voltage switching unit 12 pumps the high voltage (VPP) according to the toggled internal clock signal (CLK1). The NMOS transistor N16 is turned off and accordingly does not connect the ground (VSS) to the driving node SEL. If so, the high voltage NMOS transistor N10 is turned on so that the step-up voltage level of the output terminal Vout rises.
However, the step-up voltage generating circuit constructed above generates a very high voltage of 25V to a minimum 16.5V without any filtering unit. Accordingly, a very great ripple is generated due to the high voltage of 25V. This makes it difficult to implement ISPP.